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SY89113U
2.5V Low Jitter, Low Skew 1:12 LVDS Fanout Buffer with 2:1 Input MUX and Internal Termination
General Description
The SY89113U is a 2.5V low jitter, low skew, 1:12 LVDS fanout buffer optimized for precision telecom and enterprise server distribution applications. The input includes a 2:1 MUX for clock switchover applications. Unlike other multiplexers, this input includes a unique isolation design that minimizes channel-to-channel crosstalk. The SY89113U distributes clock frequencies from DC to >1GHz guaranteed over temperature and voltage. The SY89113U incorporates a synchronous output enable (EN) so that the outputs will only be enabled/disabled when they are already in the LOW state. CLK0 differential input includes Micrel's unique, 3-pin input termination architecture that directly interfaces to any differential signal (AC- or DC-coupled) as small as 100mV (200mVPP) without any level shifting or termination resistor networks in the signal path. CLK1 differential input includes a new version of Micrel's unique, Any-Input architecture that directly interfaces with single-ended TTL/CMOS logic (including 3.3V logic), single-ended LVPECL, differential (AC- or DC-coupled) LVDS, HSTL, CML, and LVPECL logic levels as small as 200mV (400mVPP). CLK1 input requires external termination. LVDS output swing 325mV into 100 with extremely fast rise/fall time guaranteed to be less than 250ps. The SY89113U operates from a 2.5V5% supply and is guaranteed over the full industrial temperature range of -40C to +85C. The SY89113U is part of Micrel's high-speed, Precision Edge(R) product line. All support documentation can be found on Micrel's web site at: www.micrel.com.
Precision Edge(R)
Features
* Selects between 1 of 2 inputs, and provides 12 precision, low skew LVDS output copies * Guaranteed AC performance over temperature and voltage: - DC to >1GHz throughput - <975ps propagation delay CLK0-to-Q - <250ps rise/fall time - <25ps output-to-output skew * Ultra-low jitter design: - <1psRMS random jitter - <10psPP total jitter (clock) - <1psRMS cycle-to-cycle jitter - <0.7psRMS crosstalk induced jitter * Unique, patent-pending 2:1 input MUX provides superior isolation to minimize channel-to-channel crosstalk * CLK0 input features a unique, patent-pending input termination and VT pin that accepts AC- and DCcoupled inputs (CML, LVPECL, LVDS) * CLK1 accepts virtually any logic standard: - Single-ended: TTL/CMOS (including 3.3V logic), LVPECL - Differential: LVPECL, LVDS, CML, HSTL * 325mV LVDS-compatible output swing * Power supply: 2.5V +5% * Industrial temperature range -40C to +85C * Available in 44-pin (7mm x 7mm) MLFTM package
Applications
* * * *
Precision Edge is a registered trademark of Micrel, Inc. MLF and MicroLeadFrame are trademarks of Amkor Technology, Inc. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
Multi-processor server SONET/SDH clock/data distribution Fibre Channel distribution Gigabit Ethernet clock distribution
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SY89113U
Functional Block Diagram
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SY89113U
Ordering Information(1)
Part Number SY89113UMG SY89113UMGTR(2)
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. 2. Tape and Reel.
Package Type MLF-44 MLF-44
Operating Range Industrial Industrial
Package Marking SY89113U with Pb-Free bar-line indicator SY89113U with Pb-Free bar-line indicator
Lead Finish NiPdAu Pb-Free NiPdAu Pb-Free
Pin Configuration
44-Pin MLFTM (MLF-44)
Truth Table
EN H H L
Note: 1. Transition occurs on next negative transition of the non-inverted input.
CLK_SEL L H X
Q CLK0 CLK1 L
(1)
/Q /CLK0 /CLK1 H(1)
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SY89113U
Pin Description
Pin Number 1, 6, 11, 22, 34 Pin Name GND, Exposed Pad CLK0, /CLK0 Pin Function Ground. GND pins and exposed pad must both be connected to the most negative potential of chip the ground. Differential Inputs: This input pair is a differential signal input to the device. Input accepts AC- or DC-coupled signals as small as 100mV (200mVPP). Each pin of the pair internally terminates to a VT pin through 50. Note that this input defaults to an indeterminate state if left open. Please refer to the "CLK0 Input Interface Applications" section for more details. Input Termination Center-Tap: Each side of the differential input pair CLK0, /CLK0 terminates to the VT pin. The VT pin provides a center-tap to a termination network for maximum interface flexibility. See "CLK0 Input Interface Applications" section for more details. For DC-coupled CML or LVDS inputs, the VT pin is left floating. Reference Voltage: This output biases to VCC-1.2V. It is used when AC-coupling the input CLK0. For AC-coupled applications, connect VREF-AC0 to the VT0 pin and bypass with 0.01F low ESR capacitor to VCC. See "CLK0 Input Interface Applications" section for more details. Maximum sink/source current is 1.5mA. Due to the limited drive capability, the VREF-AC0 pin is only intended to drive its respective input pin. Input Termination Pin: When CLK1 is driven by a single-ended TTL/CMOS signal, tie this pin to GND. In all other modes, let this pin float. See "CLK1 Interface Applications" section for more details. Differential Inputs: This input pair is a differential signal input to the device. This input accepts Any-Logic standard as small as 200mV (400mVPP). Note that this input defaults to an indeterminate state if left open. Tie either the true or the complement input to ground while the other input is floating. This input can be used for singleended signals (including TTL/CMOS signals from a 3.3V driver). See "CLK1 Input Interface Applications" section for more details. Reference Voltage: This output biases to VCC-1.425V. VBB1 is designed to act as a switching reference for the CLK1 and /CLK1 inputs when configured in single-ended PECL input mode. VBB1 can be used for AC-coupling of CLK1, see Figure 4d for details. Maximum sink/source current is 1.5mA. Due to the limited drive capability, the VBB1 pin is only intended to drive its respective input pin. This single-ended, TTL/CMOS-compatible input functions as a synchronous output enable. The synchronous enable ensures that enable/disable will only occur when the outputs are in a logic LOW state. Note that this input is internally connected to a 25k pull-up resistor and will default to logic HIGH state (enable) if left open. Positive power supply. Bypass with 0.1F//0.01F low ESR capacitors and place as close to the VCC pins as possible. This single-ended, TTL/CMOS-compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25k pull-up resistor and will default to logic HIGH state if open.
2, 5
3
VT0
4
VREF-AC0
7
SE-TERM
8, 10
CLK1, /CLK1
9
VBB1
12 13, 23, 28, 33, 43 44 42, 41 40, 39 38, 37 36, 35 32, 31 30, 29 27, 26 25, 24 21, 20 19, 18 17, 16 15, 14
EN
VCC CLK_SEL Q0, /Q0 Q1, /Q1 Q2, /Q2 Q3, /Q3 Q4, /Q4 Q5, /Q5 Q6, /Q6 Q7, /Q7 Q8, /Q8 Q9, /Q9 Q10, /Q10 Q11, /Q11
Differential LVDS Outputs: These LVDS output pairs are the precision, low skew copies of the selected input. Please refer to the, "Truth Table" below for details. Unused output pairs should be terminated with 100 across the pair. Each output is designed to drive 325mV into 100. See the "LVDS Output Interface Applications" section for more details.
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Absolute Maximum Ratings(1)
Supply Voltage (VCC) .......................... -0.5V to +4.0V Input Voltage (Differential Input CLK0, CLK1(4, 5)).. -0.5V to VCC Current on Reference Voltage Outputs Source or sink current on VREF-AC0, VBB1.....2mA Termination Current Source or sink current on VT0 ................100mA Input Current Source or sink current on CLK0, /CLK0 ...50mA Lead Temperature (soldering, 20 sec.) .......... +260C Storage Temperature (Ts) ................. -65C to 150C
Operating Ratings(2)
Supply Voltage (VCC).................. +2.375V to +2.625V Ambient Temperature (TA)................ -40C to +85C Package Thermal Resistance(3) MLFTM (JA) Still-Air ................................................ 24C/W MLFTM (JB) Junction-to-Board ................................. 8C/W
DC Electrical Characteristics(6)
TA = -40C to +85C, unless otherwise stated.
Symbol VCC ICC RIN RDIFF_IN VIH Parameter Power Supply Power Supply Current Input Resistance (CLK0-to-VT) Differential Input Resistance (CLK0-to-/CLK0) Input High Voltage (CLK0, /CLK0) (CLK1, /CLK1) VIL Input Low Voltage (CLK0, /CLK0) (CLK1, /CLK1) VIN Input Voltage Swing (CLK0, /CLK0) (CLK1, /CLK1) VDIFF_IN Differential Input Voltage Swing |CLK0-to-/CLK0| |CLK1-to-/CLK1| VT0 VREF-AC0 VBB1
Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. JA and JB values are determined for a 4-layer board in still-air, unless otherwise stated. 4. SE-TERM not connected. 5. Using single-ended TTL/CMOS input signals, SE-TERM connects to GND. See Figure 4f. 6. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Condition No load, max. VCC
Min 2.375
Typ 240
Max 2.625 330 55 110
Units V mA
45 90
50 100
1.2 Note 4 Note 5 0.2 1.2 0.1 Note 4 Note 5 See Figure 1a. See Figure 1a. See Figure 1b. See Figure 1b. 0.2 0 0.1 0.2 0.2 0.4
VCC VCC 3.6 VCC
V V
V V V
VCC
V V V V
CLK0-to-VT0 (CLK0, /CLK0) Output Reference Voltage Output Reference Voltage VCC-1.3 VCC-1.525 VCC-1.2 VCC-1.425
1.28 VCC-1.1 VCC-1.325
V V V
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SY89113U
LVDS Outputs DC Electrical Characteristics(7)
VCC = +2.5V 5%; TA = -40C to +85C; RL = 100 across the output pair, unless otherwise stated.
Symbol VOUT VDIFF-OUT VOCM VOS Parameter Output Voltage Swing Q, /Q Differential Output Voltage Swing Q, /Q Output Common Mode Voltage Change in VOS between complementary output states Condition See Figure 1a. See Figure 1b. Min 250 500 1.125 Typ 325 650 1.275 25 Max Units mV mV V mV
LVTTL/CMOS DC Electrical Characteristics(7)
VCC = +2.5V 5%; TA = -40C to +85C, unless otherwise stated.
Symbol VIH VIL IIH IIL
Note: 7. The circuit is designed to meet the DC specifications, shown in the above table, after thermal equilibrium has been established.
Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current
Condition
Min 2.0
Typ
Max 0.8
Units V V A A
-125 -300
30
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SY89113U
AC Electrical Characteristics(8)
VCC = +2.5V 5%; TA = -40C to + 85C, RL = 100 across the output pair, unless otherwise stated.
Symbol fMAX Parameter Maximum Operating Frequency Propagation Delay tPD CLK0-to-Q CLK1-to-Q CLK_SEL-to-Q tPD Tempco tS Differential Propagation Delay Temperature Coefficient Set-up Time EN-to-CLK0 EN-to-CLK1 Hold Time tH CLK0-to-EN CLK1-to-EN Output-to-Output Skew tSKEW Part-to-Part Skew CLK0 Part-to-Part Skew CLK1 Cycle-to-Cycle Jitter tJITTER Random Jitter (RJ) Total Jitter (TJ) Adjacent Channel Crosstalk-induced Jitter tr, tf
Notes: 8. 9. High-frequency AC-parameters are guaranteed by design and characterization. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications, set-up and hold do not apply.
Condition VOUT 200mV VIN 100mV VIN 200mV
Min 1 625 700 500
Typ
Max
Units GHz
750 900 700 90
975 1200 900
ps ps ps fs/oC
Note 9 Note 9 Note 9 Note 9 Note 10 Note 11 Note 11 Note 12 Note 13 Note 14 Note 15 At full output swing.
100 0 500 600 25 200 250 1 1 10 0.7 80 150 250
ps ps ps ps ps ps ps psRMS psRMS psPP psRMS ps
Output Rise/Fall Time (20% to 80%)
10. Output-to-output skew is measured between two different outputs under identical input transitions. 11. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs 12. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn - Tn-1 where T is the time between rising edges of the output signal. 13. Random jitter is measured with a K28.7 character pattern, measured at 12
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SY89113U
Typical Operating Characteristics
VCC = 2.5V, GND = 0, VIN = 400mV, RL = 100 across the output pair; TA = 25C, unless otherwise stated.
Functional Characteristics
VCC = 2.5V, GND = 0, VIN = 400mV, RL = 100 across the output pair; TA = 25C, unless otherwise stated.
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Single-Ended and Differential Swings
Figure 1a. Single-Ended Voltage Swing CLK0
Figure 1b. Differential Voltage Swing CLK0
Timing Diagrams
/CLK CLK /Q Q tPD
Differential In-to-Differential Out
~ ~
VCC/2 CLK_SEL /Q Q tPD tPD VCC/2
CLK_SEL-to-Differential Out
~~ ~~
EN VCC/2 /CLK CLK /Q Q tS tH VCC/2
Set-Up and Hold Time EN-to-Differential IN
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SY89113U
Input and Output Stages
Figure 2a. CLK1 Differential Input Structure
Figure 2b. CLK0 Differential Input Structure
CLK0 Input Interface Applications
option: may connect VT to VCC Figure 3a. LVPECL Interface (DC-Coupled) Figure 3b. LVPECL Interface (AC-Coupled) Figure 3c. CML Interface (DC-Coupled)
Figure 3d. CML Interface (AC-Coupled)
Figure 3e. LVDS Interface
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SY89113U
CLK1 Input Interface Applications
Figure 4a. CML, LVDS Interface (DC-Coupled)
Figure 4b. CML Interface (DC-Coupled)
Figure 4c. PECL Interface (DC-Coupled)
(See Single-Ended TTL/CMOS Recommended Resistor Table for Recommended Resistor Value R)
Figure 4d. PECL Interface (AC-Coupled)
Figure 4e. PECL Interface (Single-Ended)
Figure 4f. TTL/CMOS Interface (Single-Ended)
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Single-Ended TTL/CMOS Recommended Resistor Value
The SY89113U can be driven by a TTL/CMOS input signal. See Figure 4f. The resistor R, in Table 1, below is calculated according to the following equation:
1 R = 1.594 x - 1 5.057 x VCC -1 2 x VCC + VIH + VIL The equation above is used to determine the optimum value of R for best duty cycle.
Recommended R () 1.8V CMOS 2.5V CMOS 3.3V CMOS 261 732 1470
LVDS Output Interface Applications
LVDS specifies a small swing of 325mV typical, on a nominal 1.2V common mode above ground. The common mode voltage has tight limits to permit large variations in ground between an LVDS driver and receiver. Also, change in common mode voltage, as a function of data input, is kept to a minimum, to keep EMI low.
Figure 5a. LVDS Differential Measurement
Table 1. Single-Ended TTL/CMOS Recommended Resistors Figure 5b. LVDS Common Mode Measurement
Related Product and Support Documentation
Part Number SY89112U Function 2.5/3.3V Low Jitter, Low Skew 1:12 LVPECL Fanout Buffer with 2:1 Input MUX and Internal Termination New Products and Applications MLF
TM
Data Sheet Link http://www.micrel.com/product-info/products/SY89112U.shtml www.micrel.com/product-info/products/solutions.shtml www.amkor.com/products/notes_papers/MLFAppNote.pdf
HBW Solutions
Application Note
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SY89113U
Package Information
44-Pin MLFTM (MLF-44)
44-Pin MLFTM (MLF-44)
Package Notes: 1. Package meets Level 2 moisture sensitivity classification, and is shipped in dry pack form. 2. Exposed pads must be soldered to a ground for proper thermal management.
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SY89113U
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2005 Micrel, Incorporated.
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